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74ABT646 Octal Transceivers and Registers with 3-STATE Outputs
April 1992 Revised November 1999
74ABT646 Octal Transceivers and Registers with 3-STATE Outputs
General Description
The ABT646 consists of bus transceiver circuits with 3STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is Active LOW. In the isolation mode (control OE HIGH), A data may be stored in the B register and/or B data may be stored in the A register.
Features
s Independent registers for A and B buses s Multiplexed real-time and stored data s A and B output sink capability of 64 mA, source capability of 32 mA s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability
Ordering Code:
Order Number 74ABT646CSC 74ABT646CMSA 74ABT646CMTC Package Number M24B MSA24 MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-153, 4.4mm Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names A0-A7 B0-B7 CPAB, CPBA SAB, SBA OE DIR Description Data Register A Inputs/3-STATE Outputs Data Register B Inputs/3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Input Direction Control Input
(c) 1999 Fairchild Semiconductor Corporation
DS010978
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74ABT646
Truth Table
Inputs OE H H H L L L L L L L L DIR X X X H H H H L L L L CPAB H or L CPBA H or L SAB X X X L L H H X X X X SBA X X X X X X X L L H H Output Input Input Input Input Data I/O (Note 1) A0-A7 B0-B7 Isolation Clock An Data into A Register Clock Bn Data into B Register An to Bn--Real Time (Transparent Mode) Output Clock An Data into A Register A Register to Bn (Stored Mode) Clock An Data into A Register and Output to Bn Bn to An--Real Time (Transparent Mode) Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn Data into B Register and Output to An Function
X
X X X X
X
H or L

X X X X
X
H or L

X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Real Time Transfer A-Bus to B-Bus
Storage from Bus to Register
FIGURE 1. Real Time Transfer B-Bus to A-Bus
FIGURE 3. Transfer from Register to Bus
FIGURE 2.
FIGURE 4.
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Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Any Output in the Disable or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) twice the rated IOL (mA) -500 mA 10V -0.5V to +5.5V -0.5V to VCC -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input Clock Input 50 mV/ns 20 mV/ns 100 mV/ns -40C to +85C +4.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL VID IIH IBVI IBVIT IIL IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input Leakage Test Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current 4.75 1 1 7 100 -1 -1 Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC (Note 4) No Load 0.18 mA/MHz Max -100 10 -10 -275 50 100 250 30 50 2.5 2.5 2.0 0.55 V 0.0 Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA (Non I/O Pins) IOH = -3 mA, (An, Bn) IOH = -32 mA, (An, Bn) IOL = 64 mA, (An, Bn) IID = 1.9 A, (Non-I/O Pins) All Other Pins Grounded A A A A A A mA A A A mA A mA Max Max Max Max V IN = 2.7V (Non-I/O Pins) (Note 4) V IN = VCC (Non-I/O Pins) V IN = 7.0V (Non-I/O Pins) V IN = 5.5V (An, Bn) V IN = 0.5V (Non-I/O Pins) (Note 4) V IN = 0.0V (Non-I/O Pins)
0V-5.5V V OUT = 2.7V (An, Bn); OE = 2.0V 0V-5.5V V OUT = 0.5V (An, Bn); OE = 2.0V Max Max 0.0V Max Max Max Max V OUT = 0V (An, Bn) V OUT = VCC (An, Bn) V OUT = 5.5V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW Outputs 3-STATE; All Others GND V I = VCC - 2.1V All Other Outputs at VCC or GND Outputs OPEN OE and DIR = GND, Non-I/O = GND or VCC (Note 5) One Bit toggling, 50% duty cycle
Note 4: Guaranteed but not tested. Note 5: For 8-bit toggling, ICCD < 1.4 mA/MHz.
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74ABT646
DC Electrical Characteristics
Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage -1.2 2.5 2.2 Min Typ 0.6 -0.9 3.0 1.8 0.8 0.5 Max 0.8 Units V V V V V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL = 50 pF, RL = 500 TA = 25C (Note 6) TA = 25C (Note 6) TA = 25 (Note 7) TA = 25C (Note 8) TA = 25C (Note 8)
Note 6: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 7: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 8: Max number of data inputs (n) switching. n - 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP package) TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay SBA or SAB to An to Bn Enable Time OE to Anor Bn Disable Time OE to Anor Bn Enable Time DIR to An or B n Disable Time DIR to An or B n 200 1.7 1.7 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 3.0 3.4 2.6 3.0 3.0 3.4 3.2 3.5 3.7 3.2 3.4 3.7 3.8 3.2 5.6 5.6 4.8 4.8 5.9 5.9 6.3 6.3 6.0 6.0 6.3 6.3 6.0 6.0 VCC = +5.0V CL = 50 pF Typ Max TA = -55C to +125C VCC = 4.5V-5.5V CL = 50 pF Min 200 2.2 1.7 1.5 1.5 1.5 1.5 1.0 1.9 1.5 1.5 1.0 2.2 1.5 1.5 8.8 8.8 7.9 7.9 8.1 8.9 7.3 8.8 9.3 9.3 7.7 9.5 8.7 9.2 Max TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF Min 200 1.7 1.7 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 5.6 5.6 4.8 4.8 5.9 5.9 6.3 6.3 6.0 6.0 6.3 6.3 6.0 6.0 Max MHz ns ns ns ns Units
ns ns ns
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V CL = 50 pF Min tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Bus to Clock Hold Time, HIGH or LOW Bus to Clock Pulse Width, HIGH or LOW 1.5 1.0 3.0 Max TA = -55C to +125C VCC = 4.5V-5.5V CL = 50 pF Min 1.5 1.0 3.0 Max 3.0 1.0 4.0 TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF Min 1.5 1.0 3.0 Max ns ns ns Units
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74ABT646
Extended AC Electrical Characteristics
(SOIC Package) TA = -40C to +85C VCC = 4.5V-5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 9) Min tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Clock to Bus Propagation Delay Bus to Bus Propagation Delay SBA or SAB to An or Bn Output Enable Time OEn or DIR to An or Bn Output Disable Time OEn or DIR to An or Bn 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max 5.5 5.5 6.0 6.0 6.0 6.0 6.0 6.0 6.0 6.0 TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 1 Output Switching (Note 10) Min 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 (Note 12) Max 7.5 7.5 7.0 7.0 7.5 7.5 8.0 8.0 TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 8 Outputs Switching (Note 11) Min 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 Max 10.0 10.0 9.5 9.5 10.0 10.0 10.5 10.5 ns ns ns ns ns Units
(Note 12)
Note 9: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 10: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 11: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 12: The 3-STATE delays are dominated by the RC network (500, 250 pF) on the output and has been excluded from the datasheet.
Skew
(SOIC Package) TA = -40C to +85C VCC = 4.5V-5.5V Symbol Parameter CL = 50 pF 8 Outputs Switching (Note 13) Max tOSHL (Note 15) tOSLH (Note 15) tPS (Note 16) tOST (Note 15) tPV (Note 17) Pin to Pin Skew, HL Transitions Pin to Pin Skew, LH Transitions Duty Cycle, LH-HL Skew Pin to Pin Skew, LH/HL Transitions Device to Device Skew, LH/HL Transitions 1.3 1.0 2.0 2.0 2.5 TA = -40C to +85C VCC = 4.5V-5.5V CL = 250 pF 8 Outputs Switching (Note 14) Max 2.5 2.0 4.0 4.0 4.5 ns ns ns ns ns Units
Note 13: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 14: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 15: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). This specification is guaranteed but not tested. Note 16: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 17: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested.
Capacitance
Symbol CIN CI/O (Note 18) Parameter Input Capacitance Output Capacitance Typ 5 11 Units pF pF Conditions TA = 25C VCC = 0V (non I/O pins) VCC = 5.0V (An, Bn)
Note 18: CI/O is measured at frequency, f = 1 MHz, per MIL-STD-883, Method 3012.
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74ABT646
AC Loading
*Includes jig and probe capacitance
FIGURE 5. Standard AC Test Load
FIGURE 6. Test Input Signal Levels Input Pulse Requirements
Amplitude 3.0V
Rep. Rate 1 MHz
tW 500 ns
tr 2.5 ns
tf 2.5 ns
FIGURE 7. Test Input Signal Requirements
AC Waveforms
FIGURE 8. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 10. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 9. Propagation Delay, Pulse Width Waveforms
FIGURE 11. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT646
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA24
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74ABT646 Octal Transceivers and Registers with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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